- Collaborate with the foundry to implement the foundry certification.
- Work on the advanced foundry process nodes to create Aprisa tech files.
- Meet the foundry's requirements to pass the tech file QA.
- Communicate between Foundry and R&D to get the new feature specs done.
- Develop the initial tool flow for the new foundry process node.
- Help the field team to solve the Foundry related issues (support mutual customers) Qualifications
- Typically requires minimum of 2+ years of experience in Physical Design with mainstream P&R tools
- Should be able to understand and communicate with foundry partners and internal teams on the exact issues and requirements.
- Have basic knowledge of the physical design rules (mainly the routing layers) from the foundry.
- Understand how to analyze routing issues and DRC violations.
- Hands on experience in Physical Design (floorplan, placement, CTS and routing).
- Hands-on experience with commercial place & route tools like Synopsys-ICC2/FC, Cadence-lnnovus or Aprisa is a must.
- Tapeout experience is a plus.
- TCL, Perl or Python scripting is a plus.
- Strong verbal and written communication skills; good presentation skills
- Good problem solving and debugging skills
- Proficiency in Korean and English is required
- Bachelors in Electronics and Communication (E&C) or Electrical or Telecom Engineering
- Masters in VLSI or Microelectronics is a plus. #LI-EDA#LI-Hybrid
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